Fast optical circuit switching has significant potential to solve scaling issues with traditional packet-switch-based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. Here we present a system-level integration of a nanosecond-scale $2\times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $< 10^{-12}$) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

中文翻译：

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使用纳秒光子开关的动态可重构突发模式链路

快速光电路交换在解决传统基于分组交换的网络的扩展问题以及提高数据中心和高性能计算应用中的带宽和功率效率方面具有巨大潜力。使用快速光开关的一个困难在于，必须在每次切换事件后快速重新获取光信号，以免显着影响系统的整体吞吐量。在这里，我们提出了纳秒级的系统级集成$2\乘以 2$具有可锁定 31 ns 的 25 Gbps 突发模式接收器的硅光子开关。基于 FPGA 的新型控制平面用于生成测试数据、控制硅光子开关和突发模式接收器，并测量 12.5 和 20 Gbps 的误码。无差错链路 (BER$< 10^{-12}$) 系统级重新配置时间低于 60 ns（20 Gbps）和 90 ns（12.5 Gbps），包括位和帧同步。