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Hardware realization of a secure and enhanced s-box based speech encryption engine
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2020-03-19 , DOI: 10.1007/s10470-020-01614-z
Abdulaziz H. ElSafty , Mohammed F. Tolba , Lobna A. Said , Ahmed H. Madian , Ahmed G. Radwan

This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are introduced to stand for the chaotic range of each parameter. Moreover, the effect of each component inside the proposed encryption system is studied, and the security of the system is validated through perceptual and statistical tests. The size of the encryption key is 175 bits to meet the global standards for the optimum encryption key width (> 128). MATLAB software is used to calculate entropy, MSE, and correlation coefficient. Both chaotic circuit and encryption/decryption schemes are designed using Verilog HDL and simulated by Xilinx ISE 14.7. Xilinx Virtex 5 FPGA kit is used to realize the proposed algorithm with a throughput 0.536 of Gbit/s. The cryptosystem is tested using two different speech files to examine its efficiency.



中文翻译:

基于安全和增强的s-box语音加密引擎的硬件实现

本文提出了一种用于语音加密应用程序的安全有效的替代盒(s-box)。提议的s-box数据在每个时钟周期都会更改,以将输入信号与不同的数据交换,并根据新算法和忆阻器混沌系统在其中生成输入数据。引入了所有忆阻器混沌系统参数的分叉图,以代表每个参数的混沌范围。此外,研究了所提出的加密系统内部每个组件的作用,并通过感知和统计测试验证了系统的安全性。加密密钥的大小为175位,以满足最佳加密密钥宽度(> 128)的全球标准。MATLAB软件用于计算熵,MSE和相关系数。混沌电路和加密/解密方案均使用Verilog HDL设计,并由Xilinx ISE 14.7模拟。Xilinx Virtex 5 FPGA套件用于以0.536 Gbit / s的吞吐量实现所提出的算法。使用两个不同的语音文件对密码系统进行了测试,以检查其效率。

更新日期:2020-03-19
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