Abstract

This paper presents a wideband blocker-tolerant direct \(\varDelta \varSigma\) receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker frequencies enabling blocker attenuation, while the in-band impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. In addition, with the help of reduced gain design, near band blocker gain is minimized, further improving the blocker resilience. The receiver is designed for configurable operation from 0.7–2.7 GHz and a baseband bandwidth of 10 MHz. Simulated in a 28 nm technology, the DDSR demonstrates a maximum noise figure of 6.2 dB, and achieves a peak SNDR of 53 dB with an out-of-band 1 dB input compression point of \(-\,11\) dBm at a 100 MHz offset.

中文翻译：

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具有选择性输入阻抗匹配的宽带阻滞器弹性直接三角积分接收器

摘要

本文提出了一种宽容忍的宽带直接\（\ varDelta \ varSigma \）接收器（DDSR）。通过选择输入阻抗匹配和降低增益设计来衰减阻塞器。选择性输入阻抗曲线在阻隔器频率处提供低阻抗，从而可实现阻隔器衰减，而带内阻抗则通过来自DDSR输出的上转换正反馈被提升至匹配条件。此外，借助减小的增益设计，可以将近带阻带器的增益降至最低，从而进一步提高了阻带器的弹性。接收器设计用于0.7-2.7 GHz的可配置操作和10 MHz的基带带宽。DDSR采用28 nm技术进行仿真，显示出最大噪声系数为6.2 dB，并且在30dB的带外1 dB输入压缩点为\（-,, 11 \）  dBm时， SNDR的峰值为53 dB。100 MHz偏移