Abstract Strained Si/relaxed SiGe/Si(110) heterostructures are gaining interest because the high hole mobility of them are suitable for realization of high-performance Si-wafer-based CMOS devices. Because the theoretical hole effective mass of the (110)-oriented tensile-strained Si is less than half of that of the unstrained Si. The strained Si layer thickness is one of the parameters that determine the device characteristics, because the strain and the crystalline quality of the strained Si layer depends on it. In this study, the samples with various strained Si layer thicknesses (20–136 nm) were grown on SiGe/Si(110) structures using the solid source molecular beam epitaxy (SSMBE) method. The electrical characteristics were evaluated by the gated Hall measurements in which the Hall measurements were performed with applying gate bias voltage. We confirmed that the mobility and the density of the carriers measured in the gated Hall measurements correspond to those of the holes driven by the gate bias voltage. The hole mobility is the highest for the sample with the 20 nm thick strained Si and decreases with increasing the strained Si layer thickness. This dependence of the hole mobility can be explained as results of the reduction of the lattice strain and the increase of the crystalline defects as the strained Si layer thickness increases.

中文翻译：

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通过门控霍尔测量研究应变 Si/Relaxed SiGe/Si(110) 异质结构中的空穴迁移率

摘要 应变Si/弛豫SiGe/Si(110)异质结构因其高空穴迁移率适合实现高性能Si晶片基CMOS器件而受到关注。因为(110)取向拉伸应变Si的理论孔有效质量小于未应变Si的理论孔有效质量的一半。应变硅层厚度是决定器件特性的参数之一，因为应变硅层的应变和结晶质量取决于它。在这项研究中，使用固体源分子束外延 (SSMBE) 方法在 SiGe/Si(110) 结构上生长具有各种应变 Si 层厚度 (20-136 nm) 的样品。电气特性通过门控霍尔测量进行评估，其中霍尔测量是在施加栅极偏置电压的情况下进行的。我们确认在门控霍尔测量中测量的载流子的迁移率和密度对应于由栅极偏置电压驱动的空穴的迁移率和密度。具有 20 nm 厚应变 Si 的样品的空穴迁移率最高，并且随着应变 Si 层厚度的增加而降低。空穴迁移率的这种依赖性可以解释为随着应变硅层厚度的增加，晶格应变降低和晶体缺陷增加的结果。