当前位置: X-MOL 学术IEEE Trans. Comput. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
IEEE Transactions on Computers ( IF 3.6 ) Pub Date : 2020-04-01 , DOI: 10.1109/tc.2019.2957355
Rei Ueno , Sumio Morioka , Noriyuki Miura , Kohei Matsuda , Makoto Nagata , Shivam Bhasin , Yves Mathieu , Tarik Graba , Jean-Luc Danger , Naofumi Homma

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

中文翻译:

基于数据路径压缩的高吞吐量/门 AES 硬件架构

本文提出了支持加密和加解密的高效高级加密标准 (AES) 硬件架构。本文中介绍的新操作重新排序和寄存器重新定时技术使我们能够在没有任何延迟开销的情况下统一 SubBytes 和 InvSubBytes 中的反转电路。此外,一种用于最小化线性映射的新优化技术,称为乘法偏移,进一步提高了硬件效率。我们还提出了一个共享密钥调度数据路径,它可以在所提出的架构中即时工作。据我们所知,在传统的 AES 加密/解密和具有塔场 S 盒的加密架构中,所提出的架构具有最短的关键路径延迟,并且在单位面积吞吐量方面效率最高。所提出的基于轮的架构可以在块并行不可用的情况下执行 AES 加密(例如,密码块链接 (CBC) 模式);因此,我们的技术可以全局应用于任何类型的架构,包括流水线架构。我们通过使用 NanGate 45-nm 开放单元库的逻辑综合评估了所提出的和一些传统数据路径的性能。因此,我们可以确认,我们提出的架构比其他传统架构实现了大约 51-64% 的效率(即更高的 bps/GE)和更低的功耗/能耗。我们通过使用 NanGate 45-nm 开放单元库的逻辑综合评估了所提出的和一些传统数据路径的性能。因此,我们可以确认,我们提出的架构比其他传统架构实现了大约 51-64% 的效率(即更高的 bps/GE)和更低的功耗/能耗。我们通过使用 NanGate 45-nm 开放单元库的逻辑综合评估了所提出的和一些传统数据路径的性能。因此,我们可以确认,我们提出的架构比其他传统架构实现了大约 51-64% 的效率(即更高的 bps/GE)和更低的功耗/能耗。
更新日期:2020-04-01
down
wechat
bug