The bandwidth of a ΔΣ modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time ΔΣ modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time ΔΣ modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.

中文翻译：

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具有2.4Ghz时钟速率的100Mhz带宽80dB动态范围连续时间Δ-Σ调制器

一个的带宽Δ ＆Sigma;调制器由时钟速率由于过采样率要求的限制。作为纳米级的CMOS工艺正在迅速发展，有可能设计出宽的带宽和高动态范围的连续时间Δ ＆Sigma;调制器用于高频应用。本文提出了一种第三阶4位连续时间Δ ＆Sigma;具有单环前馈拓扑调制器。该调制器采用40 nm CMOS工艺设计，以2.4 GHz的时钟速率实现80 dB的动态范围和100 MHz的带宽。调制器从1.2 V电源消耗的功率为69.7 mW。