Discrete cosine transform (DCT) is an indispensable module in video codecs and is a major part in many video coding standards including the latest high efficiency video coding (HEVC). As the video resolution increases, both transform sizes and the number of transforms increase continuously which poses challenges to the reusability design especially in hardware implementation. This paper presents reconfigurable transform architecture to flexibly support the reusability of different transform sizes. The proposed architecture maximally reuses the hardware resources by rearranging the order of input data for different transform sizes while still exploiting the butterfly property. Furthermore, this architecture supports reconfigurable throughput according to different hardware resource requirements. By applying the proposed architecture to the field-programmable gate array (FPGA) design of HEVC core transform matrices, the synthesis results show much lower consumption of hardware resources comparing to existing methods in the literature. The implementation in Altera’s Stratix III FPGA can operate at 139 MHz and supports real-time processing of $3840\times 2160$ ultra-high definition video at a minimum of 45 f/s and up to 359 f/s for different DCT sizes.

中文翻译：

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视频编码中离散余弦变换的可重构架构

离散余弦变换 (DCT) 是视频编解码器中不可或缺的模块，是包括最新高效视频编码 (HEVC) 在内的许多视频编码标准的重要组成部分。随着视频分辨率的增加，变换大小和变换次数都在不断增加，这对可重用性设计尤其是硬件实现提出了挑战。本文提出了可重构变换架构，以灵活支持不同变换大小的可重用性。所提出的架构通过重新排列不同变换大小的输入数据的顺序，同时仍然利用蝴蝶特性，最大限度地重用硬件资源。此外，该架构支持根据不同硬件资源需求可重新配置的吞吐量。通过将所提出的架构应用于 HEVC 核心变换矩阵的现场可编程门阵列 (FPGA) 设计，综合结果表明，与文献中的现有方法相比，硬件资源消耗要低得多。Altera Stratix III FPGA 中的实现可以在 139 MHz 下运行，并支持以最低 45 f/s 和最高 359 f/s 的速度实时处理 3840 美元\乘以 2160 美元的超高清视频，适用于不同的 DCT 尺寸。