A core problem in hardware-software codesign is in the sheer size of the design space. Without a set ISA to constrain the hardware-software interface, the design space explodes. This work presents a strategy for managing the massive hardware-software design space within the domain of machine learning inference workloads and accelerators. We first propose EngineIR, a new language for representing machine learning hardware and software in a single program. Then, using equality graphs -- a data structure from the compilers literature -- we suggest a method for efficiently enumerating the design space by performing rewrites over our representation.

中文翻译：

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使用程序重写枚举硬件-软件拆分

软硬件协同设计的核心问题在于设计空间的庞大规模。如果没有一套 ISA 来约束硬件-软件接口，设计空间就会爆炸。这项工作提出了一种管理机器学习推理工作负载和加速器领域内大量硬件-软件设计空间的策略。我们首先提出了 EngineIR，这是一种用于在单个程序中表示机器学习硬件和软件的新语言。然后，使用等式图——一种来自编译器文献的数据结构——我们提出了一种通过对我们的表示进行重写来有效枚举设计空间的方法。