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An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2020-03-02 , DOI: 10.1007/s10470-020-01607-y
Hamid Mahmoodian , Mehdi Dolatshahi

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input sampling and output buffer switches. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters. The simulation results confirm that the proposed S/H circuit properly operates for the data rates of higher than 2 GS/s. In addition, the proposed S/H circuit shows 14-bit resolution, 86.29 dB of SNDR for a 0.4 Vp-p, 218.75 MHz sinusoidal input signal at 2 GS/s sampling rate.



中文翻译:

CNTFET技术中的节能采样保持电路,用于高速应用

在本文中,碳纳米管场效应晶体管(CNTFET)技术提出了一种基于米勒效应和双重采样技术的适当结合的新型节能采样保持(S / H)电路。为了提高精度并增加输入动态电压范围,引入了一种新的基于CNTFET的线性化开关电路,该电路可同时用作输入采样和输出缓冲开关。在HSPICE中使用32 nm CNTFET技术参数对拟议的电路进行了仿真。仿真结果证实了所提出的S / H电路能够以高于2 GS / s的数据速率正常工作。此外,对于0.4 Vp-p,218.75 MHz正弦输入信号(采样率为2 GS / s),建议的S / H电路显示14位分辨率,SNDR为86.29 dB。

更新日期:2020-04-20
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