The design of neuromorphic chips aims to develop electronic circuits dedicated to executing artificial neural networks, mainly by exploring parallel processing. Unsupervised learning models, such as Self-organizing Maps (SOM), may benefit from massively concurrent hardware-based implementations to meet the requirements of real-time and embedded applications. This work first presents a theoretical analysis of the algorithms implemented in hardware to compute SOM learning and recall phases. This is important because, albeit similar, the processing steps executed in hardware are not necessarily identical to those executed in software. Then, the proposed FPGA architecture entitled SOMprocessor is shown in details. The circuit of the processor explores two different computational strategies for increasing the performance of current state-of-the-art works. These computational strategies aim to improve the data flow through the processor and its flexibility to implement different network topologies. Finally, this work presents the application of the SOMprocessor to a video categorization task. The results show that topographic and quantization errors are similar between hardware and software implementations, as well as the overall accuracy. Moreover, the proposed FPGA architecture achieves acceleration of 3 to 4 orders of magnitude as compared to CPU executions.

神经形态芯片的设计旨在主要通过探索并行处理来开发专用于执行人工神经网络的电子电路。诸如自组织映射（SOM）之类的无监督学习模型可能会从大规模并发的基于硬件的实现中受益，以满足实时和嵌入式应用程序的需求。这项工作首先提出对在硬件中实现的计算SOM学习和回忆阶段的算法的理论分析。这很重要，因为尽管相似，但在硬件中执行的处理步骤不一定与在软件中执行的处理步骤相同。然后，提出的名为SOMprocessor的FPGA体系结构详细显示。处理器电路探索了两种不同的计算策略，以提高当前最新技术的性能。这些计算策略旨在改善通过处理器的数据流及其实现不同网络拓扑的灵活性。最后，这项工作介绍了SOMprocessor在视频分类任务中的应用。结果表明，硬件和软件实现之间的地形和量化误差以及总体准确性相似。此外，与CPU执行相比，拟议的FPGA架构可实现3-4个数量级的加速。