This article presents a fully integrated hybrid current- and voltage-mode three-way digital Doherty power amplifier (PA) in CMOS using a single supply with built-in large-signal phase nonlinearity compensation. The nonlinear phase responses in both current-mode digital PA (C-DPA) and voltage-mode digital PA (V-DPA) are theoretically analyzed, which are further leveraged to achieve the PA nonlinear phase compensation. To the best of our knowledge, it is the first time the amplitude modulation (AM)–phase modulation (PM) response in V-DPA is explained in detail. The PA exploits the lagging AM–PM distortion of C-DPA and leading AM–PM distortion of V-DPAs, resulting in built-in large-signal phase nonlinearity cancellation without phase pre-distortion. Moreover, the transformer-based Doherty output network provides active load modulation to both C-DPA and V-DPA, achieving a three-way Doherty PA for deep power back-off (PBO) efficiency enhancement without supply modulation. Finally, the 1.2-V single power supply for PA power cells and input drivers reduces supply complexity. As a proof-of-concept, the hybrid three-way digital Doherty PA is implemented in a 45-nm CMOS SOI process. The measurements show a 38.5% peak drain efficiency (DE), 22.4-dBm saturated output power ( ${P}$ sat), and 32.1%/18.7% DE at 3.4-/9.3-dB PBO, achieving $\times $ 1.25/ $\times $ 1.46 PBO efficiency enhancement over idealistic class-B PA PBO efficiency at 2.3 GHz. The measured AM–PM distortion is 4.7° which is state-of-the-art among DPAs with PBO efficiency enhancement. The hybrid digital Doherty PA supports 40-/10-MSym/s 64-quadrature amplitude modulation (QAM)/256-QAM at 15.3-/15.2-dBm average output power and 24.7%/23.2% average PA DE while maintaining error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) lower than −32/−32.1 dB and −30.6/−28.9 dBc without phase pre-distortion.

中文翻译：

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具有内置相位非线性补偿的 CMOS 1.2V 混合电流和电压模式三路数字 Doherty PA

本文介绍了一种完全集成的混合电流和电压模式三路数字 Doherty 功率放大器 (PA) 在 CMOS 中使用具有内置大信号相位非线性补偿的单电源。从理论上分析了电流模式数字 PA (C-DPA) 和电压模式数字 PA (V-DPA) 中的非线性相位响应，进一步利用它们来实现 PA 非线性相位补偿。据我们所知，这是第一次详细解释 V-DPA 中的幅度调制 (AM)-相位调制 (PM) 响应。PA 利用 C-DPA 的滞后 AM-PM 失真和 V-DPA 的超前 AM-PM 失真，从而在没有相位预失真的情况下实现内置大信号相位非线性消除。而且，基于变压器的 Doherty 输出网络为 C-DPA 和 V-DPA 提供有源负载调制，实现三路 Doherty PA，无需电源调制即可实现深度功率回退 (PBO) 效率增强。最后，用于 PA 功率单元和输入驱动器的 1.2V 单电源降低了电源的复杂性。作为概念验证，混合三路数字 Doherty PA 在 45 纳米 CMOS SOI 工艺中实现。测量结果显示峰值漏极效率 (DE) 为 38.5%，饱和输出功率为 22.4-dBm ( ${P}$ sat)，以及 3.4-/9.3-dB PBO 时的 32.1%/18.7% DE，实现 $\times $ 1.25/ $\times $ 1.46 PBO 效率比理想的 B 类 PA PBO 效率提高了 2.3 GHz。测量的 AM-PM 失真为 4.7°，这是具有 PBO 效率增强的 DPA 中的最新技术。混合数字 Doherty PA 支持 40-/10-MSym/s 64-正交幅度调制 (QAM)/256-QAM，平均输出功率为 15.3-/15.2-dBm，平均 PA DE 为 24.7%/23.2%，同时保持误差矢量幅度(EVM) 和相邻信道泄漏比 (ACLR) 低于 -32/-32.1 dB 和 -30.6/-28.9 dBc，无相位预失真。