This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal–oxide–semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm2 core area.

中文翻译：

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具有嵌入式 IIR 均衡器的基于 12.8 Gbaud ADC 的有线接收器

本文演示了一种用于 NRZ/PAM4 调制的基于模数转换器 (ADC) 的接收器，具有时间数字转换器 (TDC) 辅助的多位/周期异步逐次逼近寄存器 (SAR) ADC，具有嵌入式由具有有源增益的差分源跟随器驱动的 IIR 均衡滤波器。它重新使用了现有的时间交错 (TI) ADC 采样网络，并结合了有源 Gm-C 积分器以形成可调谐的 IIR 均衡器响应。该原型在 65 nm 互补金属氧化物半导体 (CMOS) 中制造，使用 12.8-Gbuad PAM4 调制方案实现了 2.43-pJ/b 的效率。八路 TI ADC 测量 4.84 峰值有效位数，功耗为 36.3 mW，同时占用 0.24 mm2 核心面积。