Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC-based digitally controlled oscillator (DCO) having a tuning range of 2 GHz, a frequency resolution of 1.2 MHz/LSB, and a low phase noise of −104 dBc/Hz at 1-MHz offset. All PLL digital functions are consolidated in a single, fully synthesized digital signal processing unit operating at 3.5 GHz or 10 $\times $ the reference clock frequency. Limit cycles are minimized without the aid of a time-to-digital converter through substantial reduction of loop latency using a look-ahead digital loop filter. Various design techniques exploiting the advanced 7-nm FinFET technology are discussed, including noise reduction and tank ${Q}$ enhancement. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analog or mixed-mode simulators. Here, the accuracy and computational burden of calculating 1/ ${f}^{\alpha }$ noise is overcome by pre-calculating the DCO and reference phase noise profiles. The results obtained from these simulation techniques show very close agreement with experimental measurements. This 7-nm FinFET PLL occupies a competitive 0.06 mm² and consumes 40 mW.

中文翻译：

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具有低于 150-fs 集成抖动的 14-GHz Bang-Bang 数字 PLL，适用于 7-nm FinFET CMOS 中的有线应用

对增加有线数据吞吐量的需求需要具有更高保真度的数千兆赫时钟源。本文演示了一个 14-GHz bang-bang 数字锁相环 (BBPLL)，它具有 143-fs rms 抖动（从 1 kHz 到 100 MHz 集成）来为 56-Gb/s PAM-4 收发器提供时钟。低抖动是通过一个液晶显示器基于数字控制振荡器 (DCO) 的调谐范围为 2 GHz，频率分辨率为 1.2 MHz/LSB，在 1-MHz 偏移时具有 -104 dBc/Hz 的低相位噪声。所有 PLL 数字功能都整合在一个单一的、完全合成的数字信号处理单元中，工作频率为 3.5 GHz 或 10 $\times $ 参考时钟频率。通过使用前瞻数字环路滤波器显着减少环路延迟，无需时间数字转换器的帮助即可最大限度地减少限制周期。讨论了利用先进的 7 纳米 FinFET 技术的各种设计技术，包括降噪和坦克 ${Q}$ 增强。使用行业标准的数字事件驱动模拟器可以准确预测闭环相位噪声性能，与模拟或混合模式模拟器相比，计算工作量显着减少。这里，计算 1/ 的准确性和计算负担 ${f}^{\alpha }$ 通过预先计算 DCO 和参考相位噪声曲线来克服噪声。从这些模拟技术获得的结果与实验测量结果非常吻合。这种 7 纳米 FinFET PLL 占据了具有竞争力的 0.06 mm ²并消耗了 40 mW。