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A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2020-03-01 , DOI: 10.1109/jssc.2019.2951384
Amr Khashaba , Ahmed Elkholy , Karim M. Megawer , Mostafa Gamal Ahmed , Pavan Kumar Hanumolu

A ring oscillator (RO)-based low-noise frequency synthesizer is presented. Phase noise degradation caused by jitter accumulation in conventional RO-based synthesizers is alleviated by increasing the update rate. To this end, multiple phases of the crystal oscillator (XO) output are generated and edge combined to produce a clock at an integer multiple of the XO frequency, which is then used as a reference clock to a conventional injection-locked clock multiplier that generates a low-noise high-frequency output clock. Unlike conventional delay-locked loop-based multiphase generators (MPGs), the proposed MPG is implemented by using a simple $RC$ network connected between the XO terminals. As a result, the proposed approach consumes little power and, more importantly, does not suffer from jitter accumulation. Inevitable phase-spacing errors caused by process, voltage, and temperature variations, and component mismatches are mitigated by using digital background calibration. Fabricated in a 65-nm CMOS process, the prototype synthesizer operates with a standard 54-MHz crystal and generates a 432-MHz clock by combining eight phases generated by the proposed MPG. Using 432-MHz clock as the reference, an injection-locked clock multiplier generates a 5-GHz output with a measured integrated output jitter of 245 fsrms. The total power consumption is 8.2 mW of which the XO frequency multiplier consumes only 2.8 mW.

中文翻译:

使用多相生成和组合技术的低噪声频率合成器

提出了一种基于环形振荡器 (RO) 的低噪声频率合成器。通过提高更新速率,可以减轻传统基于 RO 的合成器中由抖动累积引起的相位噪声劣化。为此,生成晶体振荡器 (XO) 输出的多个相位并结合边沿以生成 XO 频率整数倍的时钟,然后将其用作传统注入锁定时钟乘法器的参考时钟,该乘法器生成低噪声高频输出时钟。与传统的基于延迟锁定环的多相发生器 (MPG) 不同,所提出的 MPG 是通过使用连接在 XO 终端之间的简单 $RC$ 网络来实现的。因此,所提出的方法消耗很少的功率,更重要的是,不会受到抖动累积的影响。通过使用数字背景校准,可以减轻由工艺、电压和温度变化以及组件不匹配引起的不可避免的相位间隔误差。原型合成器采用 65-nm CMOS 工艺制造,使用标准 54-MHz 晶体运行,并通过组合提议的 MPG 生成的八个相位来生成 432-MHz 时钟。使用 432-MHz 时钟作为参考,注入锁定时钟乘法器生成 5-GHz 输出,测得的集成输出抖动为 245 fsrms。总功耗为8.2 mW,其中XO倍频器仅消耗2.8 mW。原型合成器使用标准的 54 MHz 晶体运行,并通过组合由提议的 MPG 生成的八个相位来生成 432 MHz 时钟。使用 432-MHz 时钟作为参考,注入锁定时钟乘法器生成 5-GHz 输出,测得的集成输出抖动为 245 fsrms。总功耗为8.2 mW,其中XO倍频器仅消耗2.8 mW。原型合成器使用标准的 54 MHz 晶体运行,并通过组合由提议的 MPG 生成的八个相位来生成 432 MHz 时钟。使用 432-MHz 时钟作为参考,注入锁定时钟乘法器生成 5-GHz 输出,测得的集成输出抖动为 245 fsrms。总功耗为8.2 mW,其中XO倍频器仅消耗2.8 mW。
更新日期:2020-03-01
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