This article presents a space–time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional- $N$ phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional $\Delta \Sigma $ modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional- $N$ PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1- and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps.

中文翻译：

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用于量化降噪的具有空时平均功能的 N 小数分频 PLL

本文提出了一种空时平均技术，它可以实现瞬时小数分频，从而可以显着降低小数部分的量化误差。 $N$ 锁相环 (PLL)。空间平均可以通过使用并行运行的除法器阵列来实现。它们不同的分频比是通过使用小数 $\Delta \Sigma $ 调制器 (DSM) 和动态元素匹配 (DEM) 模块。为了降低分频器功率，本文还提出了一种仅使用一个分频器和相位选择来实现空间平均的方法。原型 2.4-GHz 分数- $N$ PLL 在 40-nm CMOS 工艺中实现。测量结果表明，所提出的技术在 1 MHz 和 10 MHz 偏移处分别将相位噪声降低了 10 dB 和 21 dB，从而将集成 rms 抖动从 9.55 ps 降低到 2.26 ps。