This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.

中文翻译：

---

具有参考纹波消除技术的 10 位 120-MS/s SAR ADC

本文介绍了一种用于高速逐次逼近寄存器模数转换器 (SAR ADC) 的参考纹波消除技术，以解决参考电压稳定问题。与旨在最小化参考纹波的现有技术不同，本文提出了一个新观点：它为全尺寸参考纹波提供了一条额外的路径，以耦合到具有相反极性的比较器，因此参考纹波的影响是抵消，从而确保准确的转换结果。为了验证所提出的技术，在 40-nm CMOS 工艺中制造了一个原型 10 位 120-MS/s SAR ADC。所提出的纹波消除技术将信噪比和失真比 (SNDR) 提高了 8 dB，并将最坏情况下的积分非线性 (INL)/微分非线性 (DNL) 降低了十倍。