A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) compares the voltages at various points on the grid to a programmable reference and delivers a set of corrective 2-b up/down (UP/DN) codes (global feedback) to the distributed uREGs across the core. Inside each uREG, the UP/DN codes control a local charge pump that sets the reference for an asynchronous comparator that turns on and off a pMOS passgate with a sub-nanosecond response. To mitigate the self-generated ripple, hybrid fast/slow passgate control is employed, whereby a parallel pMOS passgate with a slew-rate-limited gate drive is used to supply the dc portion of the load current. The distributed regulator architecture includes a scheme for limiting the degree of load-sharing imbalances among its uREGs due to the VREGC comparator offsets. Adding a switched-capacitor (SC) accelerator to the charge pump of each uREG speeds up the output-voltage transitions by up to 17 $\times $ for greater dynamic voltage and frequency scaling (DVFS) savings. Line and load regulations are 9 mV/V and 1.1 mV/A, respectively. The regulator achieves a peak power efficiency of 95.2% and a peak current efficiency of 99.1%. It reaches a peak power density of 82.3 W/mm2.

中文翻译：

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LDO 微调节器的分布式网络为 14 纳米 SOI CMOS 中的 24 核微处理器提供亚微秒 DVFS 和 IR 压降补偿

低压差 (LDO) 微调节器 (uREG) 的分布式网络可感应并校正多核微处理器中电源电网上多个点的电压，以减少因 IR 压降引起的错误。电压调节器控制器 (VREGC) 将电网上各个点的电压与可编程参考进行比较，并将一组校正 2-b 向上/向下 (UP/DN) 代码（全局反馈）传递到内核上的分布式 uREG。在每个 uREG 内，UP/DN 代码控制一个本地电荷泵，该泵为异步比较器设置参考，该比较器以亚纳秒响应打开和关闭 pMOS 传输门。为了减轻自生纹波，采用混合快速/慢速传输门控制，从而使用具有压摆率限制栅极驱动的并行 pMOS 传输门来提供负载电流的直流部分。分布式稳压器架构包括一个方案，用于限制由于 VREGC 比较器偏移而导致的 uREG 之间的负载共享不平衡程度。将开关电容器 (SC) 加速器添加到每个 uREG 的电荷泵可将输出电压转换速度提高多达 17 倍，从而实现更大的动态电压和频率缩放 (DVFS) 节省。线路和负载规定分别为 9 mV/V 和 1.1 mV/A。该稳压器实现了 95.2% 的峰值功率效率和 99.1% 的峰值电流效率。它达到了 82.3 W/mm2 的峰值功率密度。将开关电容器 (SC) 加速器添加到每个 uREG 的电荷泵可将输出电压转换速度提高多达 17 倍，从而实现更大的动态电压和频率缩放 (DVFS) 节省。线路和负载规定分别为 9 mV/V 和 1.1 mV/A。该稳压器实现了 95.2% 的峰值功率效率和 99.1% 的峰值电流效率。它达到了 82.3 W/mm2 的峰值功率密度。将开关电容器 (SC) 加速器添加到每个 uREG 的电荷泵可将输出电压转换速度提高多达 17 倍，从而实现更大的动态电压和频率缩放 (DVFS) 节省。线路和负载规定分别为 9 mV/V 和 1.1 mV/A。该稳压器实现了 95.2% 的峰值功率效率和 99.1% 的峰值电流效率。它达到了 82.3 W/mm2 的峰值功率密度。