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Area-Efficient, 600V 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) for Power Converter Applications
IEEE Journal of Emerging and Selected Topics in Power Electronics ( IF 4.6 ) Pub Date : 2019-10-14 , DOI: 10.1109/jestpe.2019.2947284
Nick Yun , Justin Lynch , Woongje Sung

This article reports the demonstration of a low-voltage (<; 600V) monolithically integrated 4H-silicon carbide (SiC) MOSFET and JBS diode (JBSFET). A singlemetal and thermal treatment process were implemented to form ohmic contacts on the n+ and p+ source regions while forming the Schottky contact on the N- SiC epitaxial layer. Different layout methodologies are discussed for fabricating an energy-efficient low-voltage JBSFET by intermittently placing the JBS diode portion in the orthogonal direction to minimize the device area, hence improving the specific ON-resistance and reducing the overall chip size by 46%. A junction termination extension (JTE)-based edge termination structure (the Hybrid-JTE) was implemented to achieve a high breakdown voltage with a very low leakage current. In addition, it was investigated that the forward characteristic of the JBSFET can be further improved by adopting Ti-based metal as the Schottky contact for the JBS diode. Device design, layout approach, fabrication, electrical characterization, and future prospects of the 4H-SiC JBSFETs are discussed in this article.

中文翻译:

适用于功率转换器应用的面积有效的600V 4H-SiC JBS二极管集成MOSFET(JBSFET)

本文报道了低压(<; 600V)单片集成4H碳化硅(SiC)MOSFET和JBS二极管(JBSFET)的演示。实施了单金属和热处理工艺以在n +和p +源极区域上形成欧姆接触,同时在N-SiC外延层上形成肖特基接触。讨论了通过在正交方向上间歇性地放置JBS二极管部分以最小化器件面积来制造节能低电压JBSFET的不同布局方法,从而提高了特定的导通电阻并将整体芯片尺寸减小了46%。实现了基于结终端扩展(JTE)的边缘终端结构(Hybrid-JTE),以实现具有极低泄漏电流的高击穿电压。此外,研究表明,采用Ti基金属作为JBS二极管的肖特基接触点,可以进一步改善JBSFET的正向特性。本文讨论了4H-SiC JBSFET的器件设计,布局方法,制造,电特性和未来前景。
更新日期:2020-04-22
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