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Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging
IEEE Journal of Emerging and Selected Topics in Power Electronics ( IF 4.6 ) Pub Date : 2019-11-07 , DOI: 10.1109/jestpe.2019.2952238
Fengze Hou , Wenbo Wang , Rui Ma , Yonghao Li , Zhonglin Han , Meiying Su , Jun Li , Zhongyao Yu , Yang Song , Qidong Wang , Min Chen , Liqiang Cao , Guoqi Zhang , Braham Ferreira

In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermomechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

中文翻译:

扇出面板级PCB嵌入式SiC功率MOSFET封装

在本文中,提出了一种新型的扇出面板级印刷电路板(PCB)嵌入式封装,用于相脚碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)电源模块。进行了电热机械设计,发现最大封装寄生电感在100 kHz时约为1.24 nH。与引线键合封装相比,PCB嵌入式封装的寄生电感至少降低了87.6%。与盲孔结构相比,所提出的盲块结构的热阻最多降低了约26%,SiC MOSFET的应力降低了约45.2%。然后,开发了一种新颖的嵌入PCB的封装工艺,并分析了三个关键封装工艺。此外,分析了PCB埋入式封装对SiC MOSFET静态特性的影响,发现:1)在一定的栅源电压下,PCB埋入式封装的输出电流比SiC裸片减小。2)由于封装引起的寄生电容,SiC MOSFET的米勒电容增加;3)与SiC裸片相比,嵌入PCB的封装的非平坦米勒平台范围扩大,并且随着漏源电压的增加,非平坦米勒平台范围也扩大。最后,比较了PCB嵌入式封装和TO-247封装的开关特性。结果表明,嵌入PCB的封装具有较小的寄生电感。2)由于封装引起的寄生电容,SiC MOSFET的米勒电容增加;3)与SiC裸片相比,嵌入PCB的封装的非平坦米勒平台范围扩大,并且随着漏源电压的增加,非平坦米勒平台范围也扩大。最后,比较了PCB嵌入式封装和TO-247封装的开关特性。结果表明,嵌入PCB的封装具有较小的寄生电感。2)由于封装引起的寄生电容,SiC MOSFET的米勒电容增加;和3)与SiC裸片相比,嵌入PCB的封装的非平坦米勒平台范围扩大,并且随着漏源电压的增加,非平坦米勒平台范围也扩大。最后,比较了PCB嵌入式封装和TO-247封装的开关特性。结果表明,嵌入PCB的封装具有较小的寄生电感。
更新日期:2020-04-22
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