Reliability is an important requirement for both communication and storage systems. Due to continuous scale down of technology multiple adjacent bits error probability increases. The data may be corrupted due soft errors. Error correction codes are used to detect and correct the errors. In this paper, design of single error correction-double error detection (SEC-DED) and single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes of different data lengths have been proposed. Proposed SEC-DED and SEC-DED-DAEC codes require lower delay and power compared to existing coding schemes. Area complexity in terms of logic gates of proposed and existing codes have been presented. ASIC-based synthesis results show a notable reduction compared to existing SEC-DED codes. All the codec architectures are synthesized on ASIC platform. Performances of different SEC-DED-DAEC codes are tabulated in terms of area, power and delay.

中文翻译：

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不同长度的SEC-DED和SEC-DED-DAEC码的设计

可靠性是通信和存储系统的重要要求。由于技术的连续缩减，多个相邻位错误概率增加。数据可能因软错误而损坏。纠错码用于检测和纠正错误。本文提出了不同数据长度的单纠错-双纠错(SEC-DED)和单纠错-双纠错-双邻纠错(SEC-DED-DAEC)码的设计。与现有编码方案相比，提议的 SEC-DED 和 SEC-DED-DAEC 代码需要更低的延迟和功率。提出的和现有代码的逻辑门方面的区域复杂性已经提出。与现有的 SEC-DED 代码相比，基于 ASIC 的综合结果显示出显着减少。所有编解码器架构均在 ASIC 平台上综合。不同 SEC-DED-DAEC 码的性能在面积、功率和延迟方面被制成表格。