We present a $W$ -band four-stage power amplifier (PA) in a 65-nm CMOS using a push–pull configuration with inductive feedback neutralization which achieves the highest figure of merit (FOM) compared to the recently reported CMOS PAs. The device was gradually tapered from the output to the input stage to optimize the power-added efficiency (PAE) while achieving high power gain with compact impedance matching with a transformer (TF). Interstage conjugate matching was also carried out with a TF to design a compact high-gain PA. Working under a supply voltage of 1.2 V, the proposed PA achieves a power gain of 28.2 dB with the 3-dB gain bandwidth of 7 GHz (76.8–83.8 GHz), a saturated output power of 16.3 dBm, and a peak PAE of 14.1% at 81.6 GHz with power dissipation of 234 mW. The total chip size is 0.714 mm2, and the core size excluding pads is only 0.121 mm2.

中文翻译：

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16.3 dBm 14.1% PAE 28-dB 增益 W 波段功率放大器，具有 65-nm CMOS 中的电感反馈

我们在 65 纳米 CMOS 中使用推挽式配置和电感反馈中和，展示了 $W$ 波段四级功率放大器 (PA)，与最近报道的 CMOS PA 相比，它实现了最高的品质因数 (FOM)。该器件从输出级到输入级逐渐变细，以优化功率附加效率 (PAE)，同时通过与变压器 (TF) 的紧凑阻抗匹配实现高功率增益。还使用 TF 进行级间共轭匹配，以设计紧凑的高增益 PA。在 1.2 V 的电源电压下工作，建议的 PA 实现了 28.2 dB 的功率增益，3 dB 增益带宽为 7 GHz (76.8–83.8 GHz)，饱和输出功率为 16.3 dBm，峰值 PAE 为 14.1 % 在 81.6 GHz 时，功耗为 234 mW。总芯片尺寸为 0.714 mm2，