In this study, a SPICE model for negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and Landau-Khalatnikov (LK) equation was presented. Suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance NC VNW-FETs. A new kind of structure was proposed for NC VNW-FETs at sub-3nm node. Moreover, in order to understand and improve NC VNW-FETs, the S-shaped polarization-voltage curve (S-curve) was divided into four regions and some new design rules were proposed. By using the SPICE model, device-circuit co-optimization was implemented. The co-design of gate work function (WF) and NC was investigated. A ring oscillator was simulated to analyze the circuit energy-delay, and it shown that significant energy reduction, up to 88%, at iso-delay for NC VNW-FETs at low supply voltage can be achieved. This study gives a credible method to analysis the performance of NC based devices and circuits and reveals the potential of NC VNW-FETs in low-power applications.

中文翻译：

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基于SPICE模型的负电容垂直纳米线FET在器件-电路级的研究

在本研究中，提出了基于 BSIM-CMG 模型和 Landau-Khalatnikov (LK) 方程的负电容垂直纳米线场效应晶体管 (NC VNW-FET) 的 SPICE 模型。受到栅极长度短的限制，高性能 NC VNW-FET 缺乏可控和集成的结构。为亚 3nm 节点的 NC VNW-FET 提出了一种新型结构。此外，为了理解和改进 NC VNW-FET，将 S 形极化电压曲线（S-curve）分为四个区域，并提出了一些新的设计规则。通过使用 SPICE 模型，实现了器件-电路协同优化。研究了门功函数 (WF) 和 NC 的协同设计。模拟环形振荡器以分析电路能量延迟，结果表明能量降低显着，高达 88%，可以在低电源电压下实现 NC VNW-FET 的等延迟。这项研究提供了一种可靠的方法来分析基于 NC 的设备和电路的性能，并揭示了 NC VNW-FET 在低功率应用中的潜力。