RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. The processor applies three effective optimization methods to improve the operating frequency. These methods are instruction fetch unit optimization including pipelined branch prediction mechanism, ALU optimization, and data alignment and sign-extension optimization for data memory output. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.

中文翻译：

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RVCoreP：优化的五级流水线RISC-V软处理器

RISC-V 是一种基于 RISC 的开放式和无忠诚度指令集架构，自 2010 年开始开发，可用于 FPGA 上的高性价比软处理器。RISC-V中基本的32位整数指令集定义为RV32I，足以支持操作系统环境，适合嵌入式系统。在本文中，我们提出了一种采用五级流水线的优化 RV32I 软处理器，名为 RVCoreP。处理器采用三种有效的优化方法来提高工作频率。这些方法是取指令单元优化，包括流水线分支预测机制、ALU 优化以及数据存储器输出的数据对齐和符号扩展优化。我们在 Verilog HDL 中实现了 RVCoreP，并使用 Verilog 仿真和实际的 Xilinx Atrix-7 FPGA 板验证了行为。我们评估 IPC（每个周期的指令）、工作频率、硬件资源利用率和处理器性能。从评测结果来看，RVCoreP 相比 VexRiscv 实现了 30.0% 的性能提升，VexRiscv 是从一些相关作品中挑选出来的高性能开源 RV32I 处理器。