Through silicon via (TSV) is a crucial interconnection structure in 3‐D integrated circuits. However, protrusion and intrusion of TSV‐Cu caused by annealing could lead to cracking and failure of back‐end‐of‐line (BEOL) layers and TSV interconnects due to mismatch of coefficient of thermal expansion. In this paper, optimizations of TSV interconnects and BEOL layers under annealing process are investigated based on fracture evaluation. Influences of geometrical factors including the TSV geometry dimension, the distance between TSV and BEOL layers, and pitch size of Cu via on energy release rate and J ‐integral are studied for TSV interconnects and BEOL layers with cracks. Effect of material properties for low k dielectrics on interfacial fracture of BEOL layers and TSV interconnects is also given. Optimized geometrical factors and optimized material properties of low k dielectrics are presented in this paper. Fracture‐based method sheds a light on emerging electronic packaging optimization.

中文翻译：

---

通过断裂评估优化退火工艺中的TSV互连和BEOL层

硅穿孔（TSV）是3D集成电路中至关重要的互连结构。但是，由于热膨胀系数的不匹配，退火引起的TSV-Cu的突出和侵入可能会导致后端（BEOL）层和TSV互连的破裂和故障。本文基于断裂评估，研究了退火工艺下TSV互连和BEOL层的优化。研究了TSV互连和带有裂纹的BEOL层的几何因素，包括TSV几何尺寸，TSV和BEOL层之间的距离以及Cu过孔的间距大小对能量释放速率和J积分的影响。材料特性对低k的影响还给出了BEOL层和TSV互连件界面断裂处的电介质。本文介绍了低k电介质的最佳几何因子和最佳材料性能。基于骨折的方法揭示了新兴的电子包装优化。