This paper presents the design of a low-power discrete-time signal-folding amplifier intended for use in place of programmable-gain amplifiers (PGA) in electrocardiogram (ECG) acquisition systems. The amplifier provides a fixed high gain while preventing output signal saturation even with rail-to-rail inputs, thanks to the proposed discrete-time signal folding technique; the fixed gain eliminates the need of gain-control circuitry while the high gain helps relax the resolution requirement of the analog-to-digital converter (ADC) that follows, thus resulting in lower power consumption and design complexity for the ADC. Fabricated in a standard 0.18-$\mu$m CMOS process, the amplifier occupies an active area of 0.254 $\mathrm{mm}^2$ and consumes 2.64 $\mu$W from a 1.2-V supply voltage. While amplifying a rail-to-rail input (2.4 $V_\mathrm{pp}$ differential) with a gain of 17.8 V/V, the amplifier achieves a signal-to-noise-plus-distortion ratio (SNDR) of 71 dB, thus making it very attractive for high-fidelity ECG recording amid large input interferences.

中文翻译：

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一个2.64μW71dB SNDR离散时间信号折叠放大器，用于降低可穿戴式ECG采集系统中ADC的分辨率要求

本文介绍了一种低功率离散时间信号折叠放大器的设计，该放大器旨在替代心电图（ECG）采集系统中的可编程增益放大器（PGA）。由于采用了建议的离散时间信号折叠技术，因此即使在轨至轨输入的情况下，该放大器也能提供固定的高增益，同时还能防止输出信号饱和；固定增益消除了对增益控制电路的需求，而高增益则有助于放宽随后对模数转换器（ADC）的分辨率要求，从而降低了ADC的功耗和设计复杂性。以标准0.18-$ \ mu $在CMOS工艺中，放大器的有效面积为0.254 $ \ mathrm {mm} ^ 2 $ 消耗2.64 $ \ mu $电源电压为1.2V时为W. 放大轨到轨输入（2.4$ V_ \ mathrm {pp} $ 该放大器的增益为17.8 V / V，达到71 dB的信噪比和失真比（SNDR），因此，在输入干扰较大的情况下，对于高保真ECG记录非常有吸引力。