Noise reduction is an essential part of the signal processing for error-free analysis and critical measurements of the signal. Various robust mixed norm (RMN)-based adaptive algorithms have been reported to remove Gaussian and impulsive noise together. In this paper, a modified robust mixed norm (MRMN) with step-size scaler-based adaptive filter has been proposed to suppress the impulsive and Gaussian noise in system identification application. Further, an attempt has been made to develop an algorithm that simultaneously improves the rate of convergence and reduce the steady-state error (SSE). The proposed adaptive algorithm on an average decreases 13.2% SSE at the same initial rate of convergence, and at the same SSE, the rate of convergence is increased by 43.8% as compared to the existing mixed norm-based adaptive algorithms. Moreover, the hardware architecture of the proposed algorithm has been implemented using VHDL on various FPGA platforms. The proposed hardware implementation of the weight update block leads to high-speed realization of the adaptive filter with little increases in hardware resources. The architecture offers a maximum clock frequency of 66.53 MHz when implemented on Virtex 5 FPGA.

中文翻译：

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用于脉冲降噪的带步长缩放器自适应滤波器的 MRMN 的 FPGA 实现

降噪是信号处理的重要组成部分，可实现无差错分析和关键信号测量。据报道，各种基于鲁棒混合范数 (RMN) 的自适应算法可以一起去除高斯噪声和脉冲噪声。在本文中，提出了一种基于步长缩放器的自适应滤波器的改进鲁棒混合范数（MRMN），以抑制系统识别应用中的脉冲和高斯噪声。此外，已经尝试开发一种同时提高收敛速度和降低稳态误差 (SSE) 的算法。所提出的自适应算法在相同的初始收敛速度下平均降低了13.2%的SSE，在相同的SSE下，与现有的基于混合范数的自适应算法相比，收敛速度提高了43.8%。而且，所提出算法的硬件架构已在各种 FPGA 平台上使用 VHDL 实现。权重更新块的建议硬件实现导致自适应滤波器的高速实现，而硬件资源几乎没有增加。在 Virtex 5 FPGA 上实施时，该架构提供的最大时钟频率为 66.53 MHz。