We introduce the strictly in-order core (SIC), a timing-predictable pipelined processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC’s key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC’s timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order pipelined processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

中文翻译：

---

SIC 的设计和分析：可证明时序可预测的流水线处理器内核

我们介绍了严格有序内核 (SIC)，这是一种时序可预测的流水线处理器内核。SIC 是可证明的时序成分并且没有时序异常。这可实现精确高效的最坏情况执行时间 (WCET) 和多核时序分析。SIC 的关键基础属性是其过渡关系的单调性，在其微体系结构状态上具有自然偏序。这种单调性是通过仔细消除标准有序流水线设计中连续指令之间的一些依赖性来实现的。我们提出了一个基于可满足性模理论的形式证明框架，该框架能够自动验证 SIC 的时序可预测性。SIC 保留了流水线的大部分优点：它仅比传统的非严格有序流水线处理器慢 6-7%。