Abstract Modern computing chips are composed of multiple, simple, low-power processing cores. Increasing the number of processing cores in a single chip brings the opportunity to exploit the inherent massive level of thread parallelism and further improved performance. However, efficient allocation of applications (threads) to available cores is a complicated process. Failing to do so, the mapping can be the limiting factor for achieving better performance on a tiled chip-multiprocessor (CMP). In this paper, we propose a mathematical formulation based on mixed integer linear program (MILP) to map application threads on cores at worst-case scenario by keeping into account the spatial topology of a two-dimensional mesh (2D-mesh) Networks-on-Chip (NoC). Our model allows evaluating in absolute term the performance of different mapping and routing algorithms. The proposed analytical model is general enough to consider a different optimising policy from energy to latency and a different number of memory controllers. In the experiments, we have shown that the proposed approach can achieve up to 40% reduction over the traditional zig-zag heuristic, therefore showing that there is a range for improving application mapping.

中文翻译：

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平铺CMP的线程核心映射分析模型

摘要 现代计算芯片由多个简单、低功耗的处理核心组成。增加单个芯片中的处理内核数量带来了利用线程并行的固有大规模水平并进一步提高性能的机会。然而，将应用程序（线程）高效分配到可用内核是一个复杂的过程。否则，映射可能成为在平铺芯片多处理器 (CMP) 上实现更好性能的限制因素。在本文中，我们提出了一种基于混合整数线性规划 (MILP) 的数学公式，通过考虑二维网格 (2D-mesh) Networks-on 的空间拓扑，在最坏情况下将应用线程映射到内核上。 -芯片（NoC）。我们的模型允许以绝对方式评估不同映射和路由算法的性能。所提出的分析模型足够通用，可以考虑从能量到延迟的不同优化策略以及不同数量的内存控制器。在实验中，我们已经表明，所提出的方法可以比传统的锯齿形启发式方法减少多达 40%，因此表明存在改进应用程序映射的范围。