Redundant gates of 4-2 compressor (hereafter, it is referred as 42C) has been removed by simplification of compressor output Boolean expression, that results in power consumption minimization. Further, the proposed design is implemented in full swing gate diffusion input logic, a low-power design technique with minimum transistor count. To evaluate the performance of existing and proposed compressor designs, they are simulated using SPICE simulation at 45 nm technology model. Also, the area is calculated from their corresponding generated layouts for the same technology model. From the simulation results, it is observed that the proposed compressor has shown performance improvement in terms of power delay product by 45% than the recently reported compressor. Further, to study the performance of proposed compressor in an application environment, a 16-bit multiplier is implemented. Its simulation results confirmed that the performance improvement is consistent in the multiplier too.

中文翻译：

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用于树木倍增器的面积和节能型4-2压缩机设计

通过简化压缩机输出布尔表达式，消除了4-2压缩机的冗余门（以下称为42C），从而将功耗降至最低。此外，提出的设计是在全开栅扩散输入逻辑中实现的，这是一种晶体管数量最少的低功耗设计技术。为了评估现有和建议的压缩机设计的性能，使用SPICE仿真在45 nm技术模型上对它们进行了仿真。同样，从相同技术模型的相应生成的布局中计算出面积。从仿真结果可以看出，建议的压缩机在功率延迟乘积方面的性能比最近报告的压缩机提高了45％。此外，为了研究建议的压缩机在应用环境中的性能，实现了16位乘法器。其仿真结果证实，乘法器的性能改进也是一致的。