Model Based System Engineering (MBSE) is a renowned approach in the context of embedded systems development. It is frequently used to deal with the structural and behavioral aspects of system design. However, the verification of system design is generally performed in isolation. It is particularly true in the context of assertion based verification. Consequently, there is a huge gap between system design and its verification that seriously effects the productivity and time-to market objectives. Therefore, in this research, we target to reduce this gap by exploiting the features of MBSE and SystemVerilog assertions (SVA’s). This article introduces a novel MBSE approach to model the design verification aspects of embedded systems, along with the system design (structural and behavioral aspects). We propose SystemVerilog in Object Constraint Language (SVOCL), an OCL temporal extension for SystemVerilog, to represent the design verification requirements by means of SVA’s. As a part of research, SVOCL transformation engine has been developed to generate SVA’s code in order to automate the design verification of embedded systems. The application of SVOCL has been validated through four case studies.

中文翻译：

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通过SVOCL对嵌入式系统进行基于模型的设计验证：SystemVerilog的OCL扩展

基于模型的系统工程（MBSE）是嵌入式系统开发中的一种著名方法。它经常用于处理系统设计的结构和行为方面。但是，系统设计的验证通常是独立进行的。在基于断言的验证中尤其如此。因此，系统设计与其验证之间存在巨大差距，严重影响了生产率和上市时间目标。因此，在这项研究中，我们旨在通过利用MBSE和SystemVerilog断言（SVA）的功能来缩小这种差距。本文介绍了一种新颖的MBSE方法，用于对嵌入式系统的设计验证方面以及系统设计（结构和行为方面）进行建模。我们提出了对象约束语言（SVOCL）中的SystemVerilog（一种针对SystemVerilog的OCL时间扩展），以通过SVA表示设计验证要求。作为研究的一部分，已经开发了SVOCL转换引擎来生成SVA的代码，以使嵌入式系统的设计验证自动化。SVOCL的应用已通过四个案例研究得到验证。