In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

中文翻译：

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用于多核响应时间分析的可扩展框架

在本文中，我们介绍了一个多核响应时间分析 (MRTA) 框架，该框架将响应时间分析与依赖于上下文无关的 WCET 值分离。相反，分析直接根据对不同硬件资源的需求来制定响应时间。MRTA 框架可扩展到不同的多核架构，具有针对公共互连的多种仲裁策略，以及不同类型和安排的本地存储器。我们为单级本地数据和指令存储器（缓存或暂存器）实例化框架，用于各种存储器总线仲裁策略，包括：循环、FIFO、固定优先级、处理器优先级和 TDMA，并考虑 DRAM刷新。MRTA 框架为多核系统的时序验证提供了一种通用方法，该方法在硬件配置中是参数化的，因此可用于架构设计阶段，以比较不同硬件配置可获得的实时性能保证水平。我们以这种方式使用该框架来评估具有各种不同架构组件和策略的多核系统的性能。然后将这些结果用于组成可预测的架构，并将其与设计用于良好平均情况行为的参考架构进行比较。该比较表明，可预测架构显着更好地保证了实时性能，并且使用周期精确仿真验证了分析的精度。