This paper describes a new approximate transform for the high efficiency video coding (HEVC). A 8 × 8 discrete cosine transform (DCT) approximation is proposed and then down-sampled or expanded to generate the 4 × 4, 16 × 16, and 32 × 32 approximate matrices. The proposed 8 × 8 approximation is carried out in part by neighbourhood in order to take the advantage of adjacent pixels correlation of natural images. Hence, rather than approximating the odd basis vectors of DCT kernel by referring to their intrinsic values, we choose to quantize that by taking into account their signs and positions. The proposed approximation matrices respect the properties of transform matrices prescribed by HEVC like orthogonality and bit-length of the basis vector elements. Furthermore, they have nearly the same arithmetic complexity and hardware requirement as those of recently proposed related methods, but involve significantly less error energy. Moreover, a reconfigurable design based on the 8 × 8 approximation transform is proposed in order to allow the simultaneous computation of eight 4-, four 8-, two 16-, or one 32-point approximate DCTs. It is found that the reconfigurable design can involve nearly 26% less area-delay product (ADP) when compared with the separate non-reconfigurable designs. Experimental results obtained from FPGA prototype and HM simulations have demonstrated the advantages of the proposed transforms.

中文翻译：

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用于HEVC的高效近似核心变换及其可重配置架构

本文介绍了一种用于高效视频编码（HEVC）的新的近似变换。提出了一种8×8离散余弦变换（DCT）近似，然后进行下采样或扩展以生成4×4、16×16和32×32近似矩阵。为了利用自然图像的相邻像素相关性，建议的8×8逼近部分地通过邻域进行。因此，我们选择参考它们的符号和位置来量化它，而不是参考它们的固有值来近似DCT内核的奇数基向量。所提出的近似矩阵尊重由HEVC规定的变换矩阵的属性，例如基本矢量元素的正交性和位长。此外，它们具有与最近提出的相关方法几乎相同的算术复杂度和硬件要求，但所涉及的错误能量却少得多。此外，提出了一种基于8×8近似变换的可重构设计，以便允许同时计算8个4、4、8、2个16或一个32点近似DCT。已经发现，与单独的不可重配置设计相比，可重配置设计可减少近26％的面积延迟积（ADP）。从FPGA原型和HM仿真获得的实验结果证明了所提出的变换的优势。为了允许同时计算8个4、4、8、2、16或1个32点近似DCT，提出了一种基于8×8近似变换的可重构设计。已经发现，与单独的不可重配置设计相比，可重配置设计可减少近26％的面积延迟积（ADP）。从FPGA原型和HM仿真获得的实验结果证明了所提出的变换的优势。为了允许同时计算8个4、4、8、2、16或1个32点近似DCT，提出了一种基于8×8近似变换的可重构设计。已经发现，与单独的不可重配置设计相比，可重配置设计可减少近26％的面积延迟积（ADP）。从FPGA原型和HM仿真获得的实验结果证明了所提出的变换的优势。