PatchMatch multi-view stereo (MVS) is one method generating depth maps from multi-view images and is expected to be used for various applications such as robot vision, 3D measurement, and 3D reconstruction. The major drawback of PatchMatch MVS is its large computational amount, and its acceleration is strongly desired. However, this acceleration is prevented by two problems. First, though PatchMatch MVS estimates depth maps by propagating estimation results among neighbor pixels, it is not suitable for GPU-based acceleration. Second, since the shape of a matching window used for stereo matching is changed dynamically, reading its pixels is inefficient in memory access. This paper proposes an FPGA accelerator exploiting on-chip FIFOs efficiently to solve the propagation problem. Moreover, reading pixels of a matching window is improved by a cover window which has the fixed shape and covers the matching window. The FPGA accelerator is designed using a design tool based on Open Computing Language (OpenCL). Although parameters of PatchMatch MVS depend on object images, these parameters can be changed easily by the OpenCL-based design. The experimental results demonstrate that the FPGA implementation achieves 3.4 and 2.2 times faster processing speeds than the CPU and GPU ones, respectively, and the power-delay product of the FPGA implementation is 3.2 and 5.7% of the CPU and GPU ones, respectively.

中文翻译：

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使用OpenCL的PatchMatch多视图立体声的FPGA加速器

PatchMatch多视图立体（MVS）是一种从多视图图像生成深度图的方法，有望用于各种应用程序，例如机器人视觉，3D测量和3D重建。PatchMatch MVS的主要缺点是计算量大，并且强烈要求加速。但是，通过两个问题来防止这种加速。首先，尽管PatchMatch MVS通过在相邻像素之间传播估计结果来估计深度图，但它不适用于基于GPU的加速。其次，由于用于立体匹配的匹配窗口的形状是动态变化的，因此读取其像素在存储器访问方面效率低下。本文提出了一种FPGA加速器，它可以有效利用片上FIFO来解决传播问题。此外，通过具有固定形状并覆盖匹配窗口的覆盖窗口来改善匹配窗口的读取像素。使用基于开放计算语言（OpenCL）的设计工具设计FPGA加速器。尽管PatchMatch MVS的参数取决于对象图像，但这些参数可以通过基于OpenCL的设计轻松更改。实验结果表明，FPGA实现的处理速度分别是CPU和GPU的3.4倍和2.2倍，FPGA实现的功率延迟乘积分别是CPU和GPU的3.2和5.7％。这些参数可以通过基于OpenCL的设计轻松更改。实验结果表明，FPGA实现的处理速度分别是CPU和GPU的3.4倍和2.2倍，FPGA实现的功率延迟乘积分别是CPU和GPU的3.2和5.7％。这些参数可以通过基于OpenCL的设计轻松更改。实验结果表明，FPGA实现的处理速度分别是CPU和GPU的3.4倍和2.2倍，FPGA实现的功率延迟乘积分别是CPU和GPU的3.2和5.7％。