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An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces.
IEEE Transactions on Biomedical Circuits and Systems ( IF 3.8 ) Pub Date : 2019-12-31 , DOI: 10.1109/tbcas.2019.2963302
Omid Malekzadeh-Arasteh , Haoran Pu , Jeffrey Lim , Charles Yu Liu , An H. Do , Zoran Nenadic , Payam Heydari

This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high- $\gamma$ band (80–160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05 $\mu$ W (0.205 $\mu$ W for feature extraction only) power and occupies 0.245 ${\text{mm}}^{\text{2}}$ die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.

中文翻译:

用于基于ECoG的高密度脑机接口的节能CMOS双模式阵列架构。

本文介绍了一种用于完全植入式脑机接口系统的高效节能皮质皮质(ECoG)阵列架构。介绍了一种新颖的双模式模拟信号处理方法,该方法可以从高 $ \ gamma $信号采集的早期频段(80–160 Hz)。最初,在全频带模式操作期间,会暂时观察整个光谱范围内的大脑活动以计算数字后端的特征权重。随后,这些权重被反馈到前端,系统恢复到基带模式以执行特征提取。这种方法利用了基于功率包络提取的独特的优化信号路径,从而在模拟模块中降低了1.72倍的功耗,并为数字化和处理(本文中在片外实现)节省了多达50倍的潜在功耗。包含32通道超低功率信号采集前端的原型是在0.8 nm电源的180 nm CMOS工艺中制造的。该芯片消耗1.05$ \ mu $ 宽(0.205 $ \ mu $ W仅用于特征提取)功率,占0.245 $ {\ text {mm}} ^ {\ text {2}} $每个通道的面积。芯片测量显示出优于76.5 dB的共模抑制比(CMRR),4.09噪声效率因子(NEF)和10.04功率效率因子(PEF)。与商业采集系统相比,已经通过脑电图和ECoG信号进行了体内人体测试,以验证性能和双模式操作。
更新日期:2020-04-22
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