VLSI circuits are perceived to dissipate extra power during testing when compared with that of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost, and even cause permanent damage to the circuit under test. Thus minimization of test power has gained increased significance. This paper explores the avenues in power minimization during test application in CMOS VLSI circuits since power consumption during testing is high when compared to normal operation. Design of low transition Test Pattern Generators is one usual method adopted to reduce power consumption. In the Proposed Modified Low Transition Linear Feedback Shift Register, power dissipation during testing is reduced by minimizing the switching activity between successive test vectors by comparing the two consecutive test vectors and inserting random bit such that total number of transitions is reduced without affecting the randomness. Significant advantage of this method is reduced power consumption with reduced complexity when compared to other existing methods. Considering experimental results there is a significant reduction in power consumption up to 36.2% for ISCAS’85 combinational bench mark circuits and up to 10% for ISCAS’89 Benchmark sequential circuit with marginal increase in area overhead.

中文翻译：

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用于低功耗应用的改进的低过渡测试模式发生器

与正常功能相比，VLSI电路在测试过程中会耗散额外的功率。剧烈的热量会降低电路的一致性，增加封装成本，甚至对被测电路造成永久性损坏。因此，最小化测试功率已变得越来越重要。本文探讨了在CMOS VLSI电路中进行测试应用时将功耗最小化的途径，因为与正常操作相比，测试期间的功耗很高。低转换测试码型发生器的设计是减少功耗的一种常用方法。在建议的修改的低过渡线性反馈移位寄存器中，通过比较两个连续的测试向量并插入随机位，以最小化连续的测试向量之间的切换活动，从而降低了测试期间的功耗，从而在不影响随机性的情况下减少了转换总数。与其他现有方法相比，此方法的显着优点是减少了功耗并降低了复杂性。考虑到实验结果，ISCAS'85组合基准测试电路的功耗显着降低了36.2％，而ISCAS'89 Benchmark顺序电路的功耗则降低了10％，而面积开销却略有增加。