The accurate analog simulation of critical circuit parts is a key task in the R&D process of integrated circuits. With the increasing complexity of integrated circuits it is becoming cumulatively challenging to simulate in the analog domain and within reasonable simulation time. Previous speedup approaches of the SPICE (Simulation Program with Integrated Circuit Emphasis) analog circuit simulator included either solver improvements and speedup or model order reduction of the semiconductor devices. In this paper we present a comprehensive approach to significantly speedup a SPICE-based analog circuit simulator while keeping the single-rate characteristic of time domain simulations. The novelty of our approach consists in the combination and extension of existing approaches in a unique way, enabling fast transient SPICE-level simulations. The main component of our approach is the circuit partitioner that combines relevant aspects from circuit theory and linear algebra in a unifying way. This enables the construction of an efficient and parallel BBD (bordered block diagonal) solver. Furthermore, this BBD structure allows for intrinsic model order reduction of the partitions during the Newton iteration, transforming the Newton method to a Quasi-Newton method. For mid-sized and large-sized circuits our BBD approach leads to significant sequential and parallel accelerations of transient simulations. Additional speedup can be gained from our block-bypass strategies exploiting the latency in the partitioned circuit. Altogether our approach leads to a speedup of up to two orders of magnitude compared to the state-of-the-art KLU solver while maintaining SPICE-level accuracy.

中文翻译：

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一种用于模拟电路精确瞬态仿真的整体快速并行方法

关键电路部件的精确模拟仿真是集成电路研发过程中的关键任务。随着集成电路复杂度的增加，在合理的仿真时间内在模拟域进行仿真变得越来越困难。SPICE（具有集成电路重点的仿真程序）模拟电路模拟器的先前加速方法包括求解器的改进和半导体器件的加速或模型阶数的减少。在本文中，我们提出了一种全面的方法，可以显着加快基于SPICE的模拟电路仿真器的速度，同时保持时域仿真的单速率特性。我们方法的新颖性在于以独特的方式组合和扩展现有方法，从而实现了快速瞬态SPICE级仿真。我们方法的主要组成部分是电路分隔器，它以统一的方式结合了电路理论和线性代数的相关方面。这使得能够构建高效且并行的BBD（带边界块对角线）求解器。此外，这种BBD结构允许在牛顿迭代过程中减少分区的固有模型顺序，从而将牛顿方法转换为准牛顿方法。对于中型和大型电路，我们的BBD方法导致瞬态仿真的显着顺序和并行加速。通过利用分区电路中的等待时间，我们的块绕过策略可以提高速度。与最新的KLU求解器相比，我们的方法总共可将速度提高两个数量级，同时保持SPICE级别的精度。