High-level verification and synthesis of SystemC models has become increasingly popular as a means to reduce the high RTL verification cost of today’s complex designs. However, the saving derived from performing verification at a higher level of abstraction is largely negated if the RTL then must be completely reverified. We demonstrate how global (system-level) properties may be verified at a behavioral level in a manner that reduces the required RTL verification. Our methodology entails using high-level control models together with semantic stubs for control and data-path refinements. The consequence is that cover goals met during high-level verification are then “virtually” met (in a semantically sound fashion) for RTL verification, and need not be re-established in the RTL. Moreover, it can be significantly more efficient (in terms of required verification cycles) to meet these cover goals at the higher level. This can lead both to less costly verification and earlier debug, providing a better structured, faster and more reliable path to implementation than is possible through conventional RTL verification.

中文翻译：

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一种在 RTL 验证过程中对高级验证进行评价的方法

SystemC 模型的高级验证和综合作为降低当今复杂设计的高 RTL 验证成本的一种手段，已变得越来越流行。然而，如果 RTL 必须完全重新验证，则在更高抽象级别执行验证所带来的节省在很大程度上会被抵消。我们演示了如何以减少所需 RTL 验证的方式在行为级别验证全局（系统级）属性。我们的方法需要使用高级控制模型以及用于控制和数据路径细化的语义存根。结果是在高级验证期间满足的覆盖目标然后“虚拟”满足（以语义上合理的方式）用于 RTL 验证，并且不需要在 RTL 中重新建立。而且，在更高级别上实现这些覆盖目标可以显着提高效率（就所需的验证周期而言）。与传统的 RTL 验证相比，这可以降低验证成本和进行更早的调试，从而提供更好的结构化、更快和更可靠的实现路径。