A multi-channel biopotential recording analog front-end (AFE) with a fully integrated area-efficient driven-right-leg (DRL) circuit is presented in this paper. The proposed AFE includes 10 channels of low-noise capacitive coupled instrumentation amplifier (CCIA), one shared 10-bit SAR ADC and a fully integrated DRL to enhance the system-level common-mode rejection ratio (CMRR). The proposed DRL circuit senses the common-mode at the CCIA output so that the AFE gain is reused as the DRL loop gain. Therefore, area efficient unit-gain buffer with small averaging capacitors can be used in DRL circuit to reduce the circuit area significantly. The proposed AFE has been implemented in a standard 0.18-μm CMOS process. The DRL circuit achieved more than 85% chip area reduction compared to the state-of-art on-chip DRL circuits and maximum 60 dB enhancement to system-level CMRR. Measurement results show high/low AFE gain of 60 dB/54 dB respectively with 1 μA/channel current consumption under 1.0 V power supply. The measured AFE input-referred noise in 1 Hz − 10k Hz range is 4.2 μV _rms and the maximum system-level CMRR is 110 dB.

中文翻译：

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具有面积高效驱动右腿电路的集成多通道生物电势记录模拟前端IC。

本文提出了一种多通道生物电势记录模拟前端（AFE），它具有完全集成的面积有效的右驱动腿（DRL）电路。拟议的AFE包括10个通道的低噪声电容耦合仪表放大器（CCIA），一个共享的10位SAR ADC和一个完全集成的DRL，以增强系统级共模抑制比（CMRR）。拟议中的DRL电路在CCIA输出端检测共模，因此AFE增益被重新用作DRL环路增益。因此，在DRL电路中可以使用面积较小的平均电容小的高效单位增益缓冲器，以显着减小电路面积。拟议的AFE已通过标准的0.18-μmCMOS工艺实现。与最新的片上DRL电路相比，DRL电路减少了超过85％的芯片面积，并最大程度地提高了系统级CMRR的60 dB。测量结果表明，在1.0 V电源下，每通道电流消耗1μA时，高/低AFE增益分别为60 dB / 54 dB。在1 Hz-10k Hz范围内测得的AFE输入参考噪声为4.2μV _均方根值，最大系统级CMRR为110 dB。