Transactional memory (TM) aims at simplifying concurrent programming via the familiar abstraction of atomic transactions. Recently, Intel and IBM have integrated hardware based TM (HTM) implementations in commodity processors, paving the way for the mainstream adoption of the TM paradigm. Yet, existing HTM implementations suffer from a crucial limitation, which hampers the adoption of HTM as a general technique for regulating concurrent access to shared memory: the inability to execute transactions whose working sets exceed the capacity of CPU caches. In this article we propose P8TM, a novel approach that mitigates this limitation on IBM’s POWER8 architecture by leveraging a key combination of hardware and software techniques to support different execution paths. P8TM also relies on self-tuning mechanisms aimed at dynamically switching between different execution modes to best adapt to the workload characteristics. In-depth evaluation with several benchmarks indicates that P8TM can achieve striking performance gains in workloads that stress the capacity limitations of HTM, while achieving performance on par with HTM even in unfavourable workloads.

中文翻译：

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通过仅回滚事务和挂起/恢复扩展硬件事务内存容量

事务内存 (TM) 旨在通过熟悉的原子事务抽象来简化并发编程。最近，英特尔和 IBM 在商用处理器中集成了基于硬件的 TM (HTM) 实现，为 TM 范式的主流采用铺平了道路。然而，现有的 HTM 实现存在一个关键的限制，这阻碍了 HTM 作为一种通用技术的采用，用于调节对共享内存的并发访问：无法执行其工作集超过 CPU 缓存容量的事务。在本文中，我们提出了 P8TM，这是一种新颖的方法，它通过利用硬件和软件技术的关键组合来支持不同的执行路径来缓解 IBM POWER8 架构的这种限制。P8TM 还依赖于旨在在不同执行模式之间动态切换的自调整机制，以最好地适应工作负载特性。多个基准的深入评估表明，P8TM 可以在强调 HTM 容量限制的工作负载中实现惊人的性能提升，同时即使在不利的工作负载中也能实现与 HTM 相当的性能。