The sum of absolute difference (SAD) calculation is one of the most computing-intensive operations in video encoders compatible with recent standards, such as high-efficiency video coding (HEVC). SAD hardware architectures employ an adder tree to accumulate the coefficients from the absolute difference between two video blocks. This paper employs high-order adder compressors (HOAC) structures into SAD hardware architectures to achieve ultra-high definition (UHD) encoding in real time, using block sizes compatible with HEVC. The proposed HOAC architectures are power-efficient and enable low-power SAD hardware accelerators. Our throughput analysis shows that the HOAC-based SAD hardware architecture is capable of encoding UHD 4K (\(3840\times 2160\)) videos in real-time at 60 frames per second. The architectures were entirely designed as dedicated ASIC blocks and were synthesized to ST 65 nm CMOS standard cells. Synthesis results show that SAD architectures using 64-2, 32-2, 16-2 and 8-2 compressors built from 4-2 compressors are significantly more efficient in terms of circuit area and total power dissipation when compared with SAD architectures using conventional adders selected by a commercial logic synthesis tool.

中文翻译：

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探索用于实时UHD视频编码的绝对差分架构之和的用于降低功耗的高阶加法器压缩器

绝对差之和（SAD）计算是与最新标准（例如高效视频编码（HEVC））兼容的视频编码器中计算量最大的操作之一。SAD硬件体系结构采用加法器树来根据两个视频块之间的绝对差来累积系数。本文将高阶加法器压缩器（HOAC）结构应用于SAD硬件体系结构，以使用与HEVC兼容的块大小实时实现超高清（UHD）编码。所提出的HOAC架构具有高能效并支持低功耗SAD硬件加速器。我们的吞吐量分析表明，基于HOAC的SAD硬件体系结构能够对UHD 4K进行编码（\（3840 \ times 2160 \））实时视频，每秒60帧。该体系结构被完全设计为专用ASIC模块，并被合成为ST 65 nm CMOS标准单元。综合结果表明，与使用传统加法器的SAD架构相比，使用由4-2压缩机构建的64-2、32-2、16-2和8-2压缩机的SAD架构在电路面积和总功耗方面的效率明显更高。由商业逻辑综合工具选择。