Due to the rapid advances of technologies, the scaling of parameters are decreasing. In VLSI (Very Large Scale Integration) technology, the feature size of integrated circuits (IC) has driving reduced in terms of power, speed, area and cost characteristics. The decreasing the sizes in sub-quarter microns, spacing between the components on-chip VLSI design and the signal switching time in terms of pico seconds or even less. As a result, the signal integrity (SI) issues are occurring at higher frequencies and high data rates. The evaluation of crosstalk noise between the coupled interconnect is one of the prominent issue in designing of high-speed ICs. In this paper, investigated the crosstalk noise of coupled copper (Cu) interconnect models with analytically at 32 nm technology nodes. Also, investigated the crosstalk reduction with shield insertion technique and increasing physical spacing between the coupled lines. For the low power VLSI applications, the shield insertion technique is preferable for reducing the crosstalk effects in coupled interconnects.

中文翻译：

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高速VLSI电路的铜互连中串扰噪声的分析和最小化

由于技术的飞速发展，参数的缩放正在减小。在超大规模集成电路（VLSI）技术中，集成电路（IC）的特征尺寸在功率，速度，面积和成本特性方面都在不断缩小。亚微米级尺寸的减小，片上VLSI组件之间的间距以及信号切换时间（以皮秒或更少）为单位。结果，在较高的频率和较高的数据速率下会出现信号完整性（SI）问题。耦合互连之间的串扰噪声的评估是高速IC设计中的突出问题之一。在本文中，我们以分析方式在32 nm技术节点上研究了耦合铜（Cu）互连模型的串扰噪声。也，研究了使用屏蔽插入技术降低串扰并增加耦合线之间的物理间距。对于低功率VLSI应用，屏蔽插入技术对于减少耦合互连中的串扰效应是更可取的。