A compact, single-layered substrate-integrated waveguide (SIW) filtenna with parasitic patch is synthesized and designed. A half-mode substrate-integrated rectangular cavity (HMSIRC) is adopted as the first stage resonator to reduce the circuit size. A parasitic patch functioning as the last stage resonator as well as the radiator is arranged closely to the HMSIRC so as to enhance the operational bandwidth and facilitate the filtering performance. Two broadside radiation nulls are realized at both the upper and lower band-edges to sharpen the band-edge roll-off rate: one is generated by the interaction between the HMSIRC and the parasitic patch, and the other is introduced by placing two pairs of shorting posts under the parasitic patch. The standard filter synthesis technology is utilized to guide the filtenna design. The optimized prototype was fabricated and measured. The measured results, in good agreement with simulated values, indicated the proposed filtenna provides a 5.1% fractional bandwidth, a maximum realized gain of 6.3 dBi, and a flat passband gain response along with excellent out-of-band selectivity, even with ultralow profile $0.015~\lambda _{0}$ and small volume $0.005~\lambda _{0}^{3}$ .

中文翻译：

---

带有寄生贴片的紧凑型单层基板集成波导滤波器的设计

合成和设计了一种紧凑的单层基板集成波导 (SIW) 滤波器和寄生贴片。采用半模基板集成矩形腔（HMSIRC）作为第一级谐振器，以减小电路尺寸。用作最后一级谐振器和辐射器的寄生贴片靠近 HMSIRC 布置，以提高操作带宽并促进滤波性能。在上带边和下带边实现两个宽边辐射零点，以提高带边滚降率：一个是由 HMSIRC 和寄生贴片之间的相互作用产生的，另一个是通过放置两对寄生贴片下的短路柱。标准滤波器合成技术用于指导滤波器设计。制造并测量了优化的原型。测量结果与模拟值非常吻合，表明建议的 filtenna 提供 5.1% 的分数带宽、6.3 dBi 的最大实现增益、平坦的通带增益响应以及出色的带外选择性，即使在超低剖面情况下 $0.015~\lambda _{0}$ 和小体积 $0.005~\lambda _{0}^{3}$ .