Abstract

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 μm technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.

中文翻译：

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使用简单的低功耗ECDLL和VCDL中的额外稳定延迟的低抖动时钟乘法器

摘要

本文研究了改进的压控延迟线（VCDL），适用于边合并延迟锁定环和乘法延迟锁定环（MDLL）。抖动产生中最重要的因素之一是增加延迟单元的数量。通过在VCDL的每个级中生成更多的延迟，在每个延迟单元级中会生成具有一定系数的其他延迟，这适用于MDLL。这可以减少所提出结构的输出抖动和功耗。改进的倍频用于倍增生成的频率，与传统的ECDLL相比，可以减少占用的面积并降低功耗。由于VCDL的相位噪声受控制电压噪声的影响，因此控制电压的噪声传递函数将传递到ECDLL输出。减少来自延迟单元的噪声可以帮助降低整个系统的相位噪声。使用CMOS技术在8 MHz至1 GHz的频率范围内使用TSMC 0.13μm技术进行布局后仿真，并且在1 GHz的频率下RMS抖动为1.06 ps。减少延迟单元的数量以及使用低功率50％占空比校正器可以降低输出抖动并降低功耗。在使用1.2 V电源的快速锁定情况下，该系统在1 GHz频率下的总功耗为3.01 mW，这表明与以前的相关工作相比，结果有所改善。在1 GHz频率下为06 ps。减少延迟单元的数量以及使用低功率50％占空比校正器可以降低输出抖动并降低功耗。在使用1.2 V电源的快速锁定情况下，该系统在1 GHz频率下的总功耗为3.01 mW，这表明与以前的相关工作相比，结果有所改善。在1 GHz频率下为06 ps。减少延迟单元的数量以及使用低功率50％占空比校正器可以降低输出抖动并降低功耗。在使用1.2 V电源的快速锁定情况下，该系统在1 GHz频率下的总功耗为3.01 mW，这表明与以前的相关工作相比，结果有所改善。