Dither modulation is a well-known data hiding technique for the quality access control of the digital image. Sometimes, quality access control demands real-time hardware implementation to achieve low-power consumption, high-speed, and real time processing with greater reliability and at the same time, the scheme can be fitted with the existing consumer electronic devices. With this motivation, we proposed an efficient hardware architecture to implement a discrete cosine transform domain based quality access control scheme. The proposed very-large-scale-integration architecture is optimized by parallel processing and is implemented in a field programmable gate array. The architecture is tested over a large number of benchmark images. The scheme offers a 90% improvement in power consumption than the related implementations found in the literature. The scheme also achieves a very high throughput of 1.34 GB/s and 1.34 GB/s for the quality access control of encoder and decoder, respectively at a maximum operating frequency of 131.16 MHz, for the processing of (512 × 512) images.

中文翻译：

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基于FPGA的灰度图像质量访问控制数据隐藏方案的并行硬件实现

抖动调制是一种众所周知的数据隐藏技术，用于数字图像的质量访问控制。有时，质量访问控制需要实时硬件实现，以实现低功耗、高速、实时处理，可靠性更高，同时该方案可以适配现有的消费电子设备。出于这个动机，我们提出了一种有效的硬件架构来实现基于离散余弦变换域的质量访问控制方案。所提出的超大规模集成架构通过并行处理进行了优化，并在现场可编程门阵列中实现。该架构在大量基准图像上进行了测试。与文献中的相关实施方案相比，该方案提供了 90% 的功耗改进。