Abstract

This paper presents an all-digital 1-1 MASH \(\Delta \Sigma\) time-to-digital converter (TDC) using time-mode signal processing. A cascode time adder with a raised inverter threshold voltage is proposed to minimize the deterministic timing error caused by the current mismatch of the discharge paths of the time adder. A differential time integrator consisting of a pair of identical single-ended time integrators is proposed to minimize the effect of the nonlinearities of the single-ended time integrator. The random and deterministic timing errors of the TDC are analyzed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the TDC exhibits 40 dB per decade noise-shaping at high frequencies. The cascode-configured discharge paths and raised threshold voltage of the load inverter improve the linearity of the TDC. The TDC achieves 1.9 ps time resolution over 48–415 kHz signal band while consuming 502 μW.

中文翻译：

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通过时间模式信号处理的全数字1-1 MASHΔ-Σ时间数字转换器

摘要

本文提出了全数字1-1 MASH \（\ Delta \ Sigma \）使用时间模式信号处理的时间数字转换器（TDC）。提出了具有升高的逆变器阈值电压的共源共栅时间加法器，以最小化由时间加法器的放电路径的电流失配引起的确定性定时误差。提出了一种由一对相同的单端时间积分器组成的差分时间积分器，以最小化单端时间积分器的非线性影响。分析了TDC的随机和确定性定时误差。TDC采用IBM 130 nm 1.2 V CMOS技术设计，并使用来自Cadence Design Systems的Spectre和BSIM4器件模型进行了分析。仿真结果表明，TDC在高频下每十年出现40 dB的噪声整形。级联配置的放电路径和负载逆变器的提高的阈值电压提高了TDC的线性度。TDC在48–415 kHz信号频带上达到1.9 ps的时间分辨率，而消耗502μW。