Abstract

A high speed low power current-mode square-rooting/geometric-mean circuit is presented in this paper. The up-down topology with MOS translinear loop in sub-threshold is the basic building block of the proposed circuit which leads to lower supply voltage requirement and body effect issues. This design is also helpful to implement the square-rooting operation of a signal and geometric-mean of two variable signals both with adjustable gain. The performance has been simulated using HSPICE software in 0.18 µm TSMC (level-49 parameters) CMOS technology. Post-layout simulation results with 1-V DC supply voltage show that the maximum linearity error of 1.3%, the − 3 dB bandwidth of 21.9 MHz and maximum power consumption of 700 nW are granted. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage and temperature) variations.

中文翻译：

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基于上下拓扑的电流模式可调增益平方根/几何均值电路

摘要

本文提出了一种高速低功耗电流模式平方根/几何均值电路。亚阈值内具有MOS跨线性环路的上下拓扑是所提出电路的基本构建模块，可导致较低的电源电压要求和人体效应问题。这种设计还有助于实现信号的平方根运算和两个可变增益均可调的可变信号的几何均值。使用HSPICE软件在0.18 µm TSMC（49级参数）CMOS技术中对性能进行了仿真。使用1V DC电源电压进行布局后的仿真结果表明，最大线性误差为1.3％，− 3 dB带宽为21.9 MHz，最大功耗为700 nW。