A binary decision diagram (BDDs) is a compact data structure used to represent a Boolean function, which facilitates scalable constructions of Boolean functions using reversible logic gates. Motivated by the scalable synthesis approach, this paper proposes an effective scheme for transforming the BDD representation of a Boolean function into a reversible circuit composed by reversible logic elements. Unlike a logic gate, a reversible logic element carries a memory to record a finite number of states. Especially, logic circuits composed by reversible elements can operate in asynchronous mode, thereby no need of a clock signal to drive all elements operating simultaneously.

二进制决策图（BDD）是一种紧凑的数据结构，用于表示布尔函数，它有助于使用可逆逻辑门进行布尔函数的可伸缩构造。基于可扩展的综合方法，本文提出了一种有效的方案，可以将布尔函数的BDD表示转换为由可逆逻辑元素组成的可逆电路。与逻辑门不同，可逆逻辑元件带有一个存储器以记录有限数量的状态。特别地，由可逆元件组成的逻辑电路可以以异步模式操作，从而不需要时钟信号来驱动所有元件同时操作。