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A High Throughput Network Processor Architecture for Latency Critical Applications
IEEE Micro ( IF 2.8 ) Pub Date : 2020-01-01 , DOI: 10.1109/mm.2019.2958896
Sourav Roy , Arvind Kaushik , Rajkumar Agrawal , Joseph Gergen , Wim Rouwet , John Arends

This article presents the recent advancements on the Advanced IO Processor (AIOP), a network processor architecture designed by NXP Semiconductors. The AIOP is a multicore accelerated computing architecture where each core is equipped with dedicated hardware for rapid task switching on every hardware accelerator call. A hardware preemption controller snoops on the accelerator completions and sends task preemption requests to the cores, thus reducing the latency of real-time tasks. A technique of priority thresholding is used to avoid latency uncertainty on lower priority tasks and head-of-line blocking. In this way, the AIOP handles the conflicting requirements of high throughput and low latency for next-generation wireless applications such as WiFi and 5G. In presence of frequent preemptions, the throughput reduces by only 3% on AIOP, compared to 25% on a similar network processor. Moreover, the absolute throughput and latency numbers are 2X better. The area and power overhead of adding hardware task-scheduling and preemption is only about 3%.

中文翻译:

用于延迟关键应用的高吞吐量网络处理器架构

本文介绍了高级 IO 处理器 (AIOP) 的最新进展,这是一种由恩智浦半导体设计的网络处理器架构。AIOP 是一种多核加速计算架构,其中每个核都配备了专用硬件,用于在每次硬件加速器调用时进行快速任务切换。硬件抢占控制器监听加速器完成并向内核发送任务抢占请求,从而减少实时任务的延迟。使用优先级阈值技术来避免较低优先级任务和队头阻塞的延迟不确定性。通过这种方式,AIOP 可以处理 WiFi 和 5G 等下一代无线应用的高吞吐量和低延迟的冲突要求。在频繁抢占的情况下,AIOP 上的吞吐量仅降低 3%,相比之下,在类似的网络处理器上为 25%。此外,绝对吞吐量和延迟数要好 2 倍。添加硬件任务调度和抢占的面积和功耗开销仅为 3% 左右。
更新日期:2020-01-01
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