Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root. These iterative algorithms present a good trade-off in terms of performance, area and power. We present a floating-point division and square root unit, which implements a radix-64 floating-point division and a radix-16 floating-point square root. To have an affordable implementation, each radix-64 division iteration and radix-16 square root iteration are made of simpler radix-4 iterations: 3 radix-4 iterations in division and 2 in square root. Speculation is used between consecutive radix-4 iterations to get a reduced timing. There are three different parts in digit-recurrence implementations: initialization, digit iterations, and rounding. The digit iteration is the iterative part and it uses the same logic for several cycles. Division and square root share partially the initialization and rounding stages, whereas each one has different logic for the digit iterations. The result is a low-latency floating-point divider and square root, requiring 11, 6, and 4 cycles for double, single and half-precision division with normalized operands and result, and 15, 8 and 5 cycles for square root. One or two additional cycles are needed in case of subnormal operand(s) or result.

中文翻译：

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低延迟浮点除法和平方根单元

数字循环算法广泛用于实际微处理器中以计算浮点除法和平方根。这些迭代算法在性能、面积和功耗方面表现出良好的权衡。我们提出了一个浮点除法和平方根单元，它实现了基数 64 浮点除法和基数 16 浮点平方根。为了获得经济实惠的实现，每个基数 64 除法迭代和基数 16 平方根迭代都由更简单的基数 4 迭代组成：除法 3 基 4 迭代和平方根 2 基迭代。在连续的基数 4 迭代之间使用推测来减少时序。数字循环实现分为三个不同的部分：初始化、数字迭代和舍入。数字迭代是迭代部分，它在几个循环中使用相同的逻辑。除法和平方根部分共享初始化和舍入阶段，而每个阶段都有不同的数字迭代逻辑。结果是一个低延迟的浮点除法器和平方根，对于具有归一化操作数和结果的双精度、单精度和半精度除法需要 11、6 和 4 个周期，对于平方根需要 15、8 和 5 个周期。如果操作数或结果不正常，则需要一两个额外的周期。