In this article, we initially present a hybrid spin-CMOS polymorphic logic gate (HPLG) using a novel 5-terminal magnetic domain wall motion device. The proposed HPLG is able to perform a full set of 1and 2-input Boolean logic functions (i.e., NOT, AND/NAND, OR/NOR, and XOR/XNOR) by configuring the applied keys. We further show that our proposed HPLG could become a promising hardware security primitive to address IC counterfeiting or reverse engineering by logic locking and polymorphic transformation. The experimental results on a set of ISCAS-89, ITC-99, and École Polytechnique Fédérale de Lausanne (EPFL) benchmarks show that HPLG obtains up to 51.4% and 10% average performance improvements on the power-delay product (PDP) compared with recent non-volatile logic and CMOS-based designs, respectively. We then leverage this gate to realize a novel processing-in-memory architecture (HPLG-PIM) for highly flexible, efficient, and secure logic computation. Instead of integrating complex logic units in cost-sensitive memory, this architecture exploits a hardware-friendly approach to implement the complex logic functions between multiple operands combining a reconfigurable sense amplifier and an HPLG unit to reduce the latency and the power-hungry data movement further. The device-to-architecture co-simulation results for widely used graph processing tasks running on three social network data sets indicate roughly 3.6× higher energy efficiency and 5.3× speedup over recent resistive RAM (ReRAM) accelerators. In addition, an HPLG-PIM achieves ~4× higher energy efficiency and 5.1× speedup over recent processing-in-DRAM acceleration methods.

中文翻译：

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混合自旋 CMOS 多态逻辑门在内存计算中的应用


在本文中，我们首先提出了一种使用新型 5 端磁畴壁运动器件的混合自旋 CMOS 多态逻辑门 (HPLG)。所提出的 HPLG 能够通过配置应用的键来执行全套 1 和 2 输入布尔逻辑功能（即 NOT、AND/NAND、OR/NOR 和 XOR/XNOR）。我们进一步表明，我们提出的 HPLG 可以成为一种有前途的硬件安全原语，通过逻辑锁定和多态转换来解决 IC 伪造或逆向工程问题。一组 ISCAS-89、ITC-99 和洛桑联邦理工学院 (EPFL) 基准测试的实验结果表明，与相比，HPLG 在功率延迟乘积 (PDP) 上获得了高达 51.4% 和 10% 的平均性能提升分别是最近的非易失性逻辑和基于 CMOS 的设计。然后，我们利用这个门来实现一种新颖的内存处理架构（HPLG-PIM），以实现高度灵活、高效和安全的逻辑计算。该架构不是将复杂的逻辑单元集成在成本敏感的存储器中，而是利用硬件友好的方法来实现多个操作数之间的复杂逻辑功能，结合可重新配置的读出放大器和 HPLG 单元，以进一步减少延迟和高耗电的数据移动。在三个社交网络数据集上运行的广泛使用的图形处理任务的设备到架构联合仿真结果表明，与最近的电阻式 RAM (ReRAM) 加速器相比，能源效率提高了大约 3.6 倍，加速速度提高了 5.3 倍。此外，与最新的 DRAM 处理加速方法相比，HPLG-PIM 的能效提高了约 4 倍，加速速度提高了 5.1 倍。